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www.fairchildsemi.com ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/12/11 AN-9735 design guideline for led lamp control using primary- side regulated flyback converter, fan103 & fsez1317 introduction many led lamp systems use the flyback converter topology. in applications where precise output current regulation is required, current sensing in the secondary side is always necessary, which resu lts in additional sensing loss. for power supply designers struggling to meet increasing regulatory pressures, the output current sensing is a daunting design challenge. primary-side regulation (psr) for power supplies can be an optimal solution for compliance and cost in led lamp systems. primary-side regulation controls the output voltage and current precisely with information in the primary side of the led lamp controller only. this removes the output current sensing loss and elimin ates all secondary-feedback circuitry. this facilitates a higher efficiency power supply design without incurring tremendous costs. fairchild semiconductor pwm psr controller fan103 and fairchild power switch (fps?) (mosfet + controller, ez-psr) fsez1317 significantly simplify meeting tighter efficiency requirements with fewer external components. this application note presen ts design considerations for led lamp systems employing fairchild semiconductor components. it includes designing the transformer and output filter, selecting the components, and implementing constant-current control. the step-by-step procedure completes a power supply design. the design is verified through an experimental prototype converter using fsez1317. figure 1 shows the typical application circuit for an led lamp using fsez1317. figure 1. typical application circuit
AN-9735 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/12/11 2 operation principle of primary-side regulation figure 2 shows typical waveforms of a flyback converter. generally, discontinuous conduction mode (dcm) operation is preferred for prim ary-side regulation since it allows better output regulation. the key of primary-side regulation is how to obtain output voltage and current information without directly sensing them. once these values are obtained, the control can be accomplished by the conventional feedback compensation method. i ds i f t on t dis t s v a stage i stage ii stage iii stage i i pk i o = i f_avg s a f n n v ? s p pk n n i ? s a o n n v ? figure 2. key waveforms of psr flyback converter the operation principles of dcm flyback converter are: stage i during the mosfet on time (t on ), input voltage (v dl ) is applied across the primary-side inductor (l m ). then mosfet current (i ds ) increases linearly from zero to the peak value (i pk ). during this time, the energy is drawn from the input and stored in the inductor. stage ii when the mosfet is turned off, the energy stored in the inductor forces the rectifier diode (d f ) to be turned on. during the diode conduction time (t dis ), the output voltage (v o ), together with diode forward-voltage drop (v f ), are applied across the secondary-side inductor and the diode current (i f ) decreases linearly from the peak value to zero. at the end of t dis , all the energy stored in the inductor has been delivered to the output. stage iii when the diode current reach es zero, the transformer auxiliary winding voltage (v a ) begins to oscillate by the resonance between the primary-side inductor (l m ) and the output capacitor of mosfet. design procedure in this section, a design pr ocedure is presented using the schematic in figure 3 as a reference. figure 3. cv & cc operation area [step-1] estimate the efficiencies figure 3 shows the cv & cc operation area. to optimize the power stage design, the e fficiencies and input powers should be specified for operating point a (nominal output voltage and current), b (70% of nominal output voltage), and c (minimum output voltage). 1. estimated overall efficiency ( ) for operating points a, b, and c: the overall power conversion efficiency should be estimated to cal culate the input power. if no reference data is available, set = 0.7 ~ 0.75 for low-voltage output applications and = 0.8 ~ 0.85 for high-voltage output applications. 2. estimated primary-side efficiency ( p ) and secondary-side efficiency ( s ) for operating points a, b, and c. figure 4 shows the definition of primary- side and secondary-side efficiencies, where the primary-side efficiency is for the power transfer from ac line input to the transformer primary side, while the secondary-side efficiency is for the power transfer from the transformer primary side to the power supply output. the typical values for the primary-side and secondary-side efficiencies are given as: v v o s p 10 ; , 3 2 3 1 ? ? ? ? ? ? ? (1)
AN-9735 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/12/11 3 v v o s p 10 ; , 3 1 3 2 ? ? ? ? ? ? ? (2) figure 4. primary- and secondary-side efficiency with the estimated overall efficiency, the input power at nominal output is given as: ? n o n o in i v p ? ? (3) where v o n and i o n are the nominal output voltage and current, respectively. the input power of transformer at nominal output is given as: s n o n o t in i v p ? ? ? _ (4) when the output voltage drops below 70% of its nominal value, the frequency is reduc ed to 33khz to prevent ccm operation. thus, the transformer should be designed for dcm both at 70% of nominal output voltage and minimum output voltage. as output voltage reduces in cc mode, the efficiency also drops. to optimize the transformer design, it is necessary to estimate the efficiencies prop erly at 70% of nominal output voltage and minimum output voltage conditions. the overall efficiency at 70% of nominal output voltage (operating point b) can be approximated as: n o f n o f n o n o b v v v v v v ? ? ? ? ? ? ? 7 . 0 7 . 0 @ ? ? (5) where v f is diode forward-voltage drop. the secondary-side efficiency at 70% of nominal output voltage (operating point b) can be approximated as: n o f n o f n o n o s b s v v v v v v ? ? ? ? ? ? ? 7 . 0 7 . 0 @ ? ? (6) then, the power supply input power and transformer input power at 70% nominal output voltage (operating point b) are given as: b n o n o b in i v p @ @ 7 . 0 ? ? ? ? (7) b s n o n o b t in i v p @ @ _ 7 . 0 ? ? ? ? (8) the overall efficiency at the minimum output voltage (operating point c) can be approximated as: n o f n o f o o c v v v v v v ? ? ? ? ? min min @ ? ? (9) where, vo min is the minimum output voltage. the secondary-side efficiency at minimum output voltage (operating point c) can be approximated as: n o f n o f o o s c v v v v v v ? ? ? ? ? min min @ ? ? (10) then, the power supply input power and transformer input power at the minimum output voltage (operating point c) are given as: c n o o c in i v p @ min @ ? ? ? (11) c s n o o b t in i v p @ min @ _ ? ? ? (12) [step-2] determine the dc link capacitor (c dl ) and the dc link voltage range it is typical to select the dc link capacitor as 2-3f per watt of input power for universal input range (90 ~ 265v rms ) and 1f per watt of input power for european input range (195 ~ 265v rms ). with the dc link capacitor chosen, the minimum dc link voltage is obtained as: l dl ch in line dl f c d p v v ? ? ? ? ? ) 1 ( ) ( 2 2 min min (13) where v line min is the minimum line voltage, c dl is the dc link capacitor, f l is the line frequency, and d ch is the dc link capacitor charging duty ratio defined as shown in figure 5, which is typically about 0.2.
AN-9735 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/12/11 4 2 1 t t d ch ? figure 5. dc link voltage waveforms the maximum dc link voltage is given as: max max 2 line dl v v ? ? (14) where v line max is the maximum line voltage. the minimum input dc link voltage at 70% nominal output voltage are given as: l dl ch b in line b dl f c d p v v ? ? ? ? ? ) 1 ( ) ( 2 @ 2 min min @ (15) the minimum input dc link voltage at minimum output voltage are given as: l dl ch c in line c dl f c d p v v ? ? ? ? ? ) 1 ( ) ( 2 @ 2 min min @ (16) [step-3] determine the transformer turns ratio figure 6 shows the mosfet drain-to-source voltage waveforms. when the mosfet is turned off, the sum of the input voltage (v dl ) and the output voltage reflected to the primary is imposed across the mosfet as: ro dl nom ds v v v ? ? max (17) where v ro is reflected output voltage defined as: ?? f o p s ro v v n n v ? ? ? (18) where v f is the diode forward voltage drop and n p and n s are number of turns for the primary side and secondary side, respectively. when the mosfet is turned on, the output voltage, together with input voltage reflected to the secondary, are imposed across the diode as: max dl p s o f v n n v v ? ? ? (19) as observed in equations (5) and (6), increasing the transformer turns ratio (n p /n s ) results in increased voltage of mosfet, while it leads to reduced voltage stress of rectifier diode. therefore, the transformer turns ratio (n p /n s ) should be determined by the compromise between mosfet and diode voltage stresses. when determining the transformer turns ratio, the voltage overshoot (v os ) on drain voltage should be also considered. the maximum voltage stress of mosfet is given as: os ro dl ds v v v v ? ? ? max max (20) for reasonable snubber design, voltage overshoot (v os ) is typically 1~1.5 times the reflected output voltage. it is also typical to have a margin of 15~20% of breakdown voltage for maximum mosfet voltage stress. s p f o n n v v ? ? ) ( figure 6. voltage stress of mosfet the transformer turns ratio between the auxiliary winding and secondary winding (n a /n s ) should be determined by considering the permissible ic supply voltage (v dd ) range and minimum output voltage in constant current. when the led operates in constant current, v dd is changed, together with the output voltage, as seen figure 7. the overshoot of auxiliary winding voltage caused by the leakage inductance also affects the v dd . v dd voltage at light-load condition, where the overshoot of auxiliary winding voltage is negligible, is given as: ?? fa f o s a v v v n n vdd ? ? ? ? 1 min (21) the actual v dd voltage at heavy load is higher than equation (21) due to the overshoot by the leakage inductance, which is proportional to the voltage overshoot of mosfet drain-to-source voltage shown in figure 7. considering the effect of voltage overshoot, the v dd voltages for nominal output voltage and minimum output voltage are given as: fa os p s f o s a v v n n v v n n vdd ? ? ? ? ? ? ? ? ? ? ? ? ? ? max (22) fa os p s f o s a v v n n v v n n vdd ? ? ? ? ? ? ? ? ? ? ? ? ? ? min 2 min (23) where v fa is the diode forward-voltage drop of auxiliary winding diode.
AN-9735 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/12/11 5 figure 7. v dd and winding voltage [step-4] design the transformer figure 8 shows the definition of mosfet conduction time (t on ), diode conduction time (t dis ), and non-conduction time (t off ). the sum of mosfet conduction time and diode conduction time at 70% of nominal output voltage is obtained as: ? ? ? ? ? ? ? ? ? ? ? ? ? ? f o b dl p s b on b dis b on v v v n n t t t 7 . 0 1 min @ @ @ @ (24) the first step in transformer design is to determine how much non-conduction time (t off ) is allowed in dcm operation. once the t off is determined, by considering the frequency variation caused by frequency hopping and its own tolerance, the mosfet condu ction time is obtained as: f o b dl p s b off s b on v v v n n t f t ? ? ? ? ? ? 7 . 0 1 1 min @ @ @ (25) figure 8. definition of t on , t dis , and t off transformer primary-side indu ctance can be calculated as: b t in s b on b dl m p f t v l @ _ 2 @ min @ 2 ) ( ? ? ? ? (26) the maximum peak-drain current can be obtained at the nominal output condition as: s m t in pk ds f l p i ? ? ? _ 2 (27) the mosfet conduction time at the nominal output condition is obtained as: min dl m pk ds on v l i t ? ? (28) the minimum number of turns for the transformer primary side to avoid the core saturation is given by: e sat pk ds m p a b i l n ? ? ? min (29) where a e is the cross-sectional area of the core in m 2 and b sat is the saturation flux density in tesla. figure 9 shows the typical characteristics of ferrite core from tdk (pc40). since the saturation flux density (b sat ) decreases as the temperature rises, the high-temperature characteristics should be c onsidered when it comes to charger in enclosed case. if th ere is no reference data, use b sat =0.25~0.3t. once the turns ratio is obtained, determine the proper integer for n s so that the resulting n p is larger than n p min obtained from equation (29). figure 9. typical b-h curves of ferrite core (tdk/pc40)
AN-9735 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/12/11 6 dcm operation at minimum output voltage should be also checked. the mosfet conduction time at minimum output voltage is given as: sr m c t in c dl c on f l p v t ? ? ? ? @ _ min @ @ 2 1 (30) where f sr is the reduced switching frequency to prevent ccm operation. then, the non-conduction time at minimum output voltage is given as: ) 1 ( 1 min min @ @ @ f o c dl s p c on sr c off v v v n n t f t ? ? ? ? ? (31) the non-conduction time should be larger than 3s (10% of the switching period), considering the tolerance of the switching frequency. [step-5] calculate the voltage and current of the switching devices primary-side mosfet the voltage stress of the mosfet was discussed when determining the turns ratio in step-3. assuming that drain- voltage overshoot is the same as the reflected output voltage, maximum drain voltage is given as: os ro dl ds v v v v ? ? ? max max (32) the rms current though the mosfet is given as: 3 s on pk ds rms ds f t i i ? ? ? (33) secondary-side diode the maximum reverse voltage and the rms current of the rectifier diode are obtained, respectively, as: max dl p s n o f v n n v v ? ? ? (34) s p ro dl rms ds rms f n n v v i i ? ? ? min (35) [step-6] output voltage and current setting the nominal output current is determined by the sensing resistor value and transformer turns ratio as: 5 . 8 ? ? ? n o s p sense i n n r (37) the voltage divider r 1 and r 2 should be determined such that v s is 2.5v at the end of diode current conduction time, as shown in figure 8. 1 2 1 ? ? ? s a ref n o n n v v r r (38) select 1% tolerance resistor for better output regulation. it is recommended to place a bypass capacitor of 22~68pf closely between the vs pin and the gnd pin to bypass the switching noise and keep th e accuracy of the sampled voltage for cv regulation. the value of the capacitor affects the load regulation and constant-current regulation. figure 10 illustrates the measured waveform on the vs pin with a different vs capacitor. if a higher value vs capacitor is used, the charging time becomes longer and the sampled voltage is higher than the actual value. figure 10. effect on sampling voltage with different vs capacitor [step-7] determine the output filter stage the peak to peak ripple of capacitor current is given as: pk ds s p co i n n i ? ? ? (39) the voltage ripple on the output is given by: c co co n o co o dis co o r i i i i c t i v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 (40) sometimes it is impossible to meet the ripple specification with a single output capacitor (c o ) due to the high esr (r c ) of the electrolytic capacitor. additional lc filter stages (post filter) can be used. when using the post filters, do not to place the corner frequency too low. too low a corner frequency may make the system unstable or limit the control bandwidth. it is typical to set the corner frequency of the post filter at around 1/10 ~ 1/5 of the switching frequency.
AN-9735 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/12/11 7 [step-8] cable voltage-drop compensation when the load is far away from output, the output voltage needs to compensate for voltage drop. fan103 and fsez1317 have cable voltage-drop compensation that can be programmed by a resistor on the comr pin, as shown in table 1. if the comr is not used, such as for led bulb, it needs be to connected to gnd. table 1. cable compensation % of voltage drop compensation comr resistor 7% open 6% 900 ? 5% 380 ? 4% 230 ? 3% 180 ? 2% 145 ? 1% 100 ? 0% 45 ? [step-9] design rcd snubber in primary side when the power mosfet is turned off, there is a high- voltage spike on the drain du e to the transformer leakage inductance. this excessive voltage on the mosfet may lead to an avalanche breakdown and, eventually, failure of the device. therefore, it is n ecessary to use an additional network to clamp the voltage. the rcd snubber circuit and mosfet drain-voltage waveform are shown in figure 6. the rcd snubber network absorbs the current in the leakage inductance by turning on the snubber diode (d sn ) once the mosfet drain voltage exceeds the voltage of cathode of d sn . in the analysis of snubber network, it is assumed that the snubber capacitor is large enough that its voltage does not change significantly during one switching cycle. the snubber capacitor should be ceramic or a material that offers low es r. electrolytic or tantalum capacitors are unacceptable for these reasons. the snubber capacitor voltage at full-load condition (v sn ) is given as: os ro sn v v v ? ? (41) the power dissipated in the snubber network is obtained as: s os sn sn pk ds lk sn sn sn f v v v i l r v p ? ? ? ? ? ? ? 2 2 ) ( 2 1 (42) where i ds pk is peak-drain current at full load, l lk is the leakage inductance, v sn is the snubber capacitor voltage at full load, and r sn is the snubber resistor. the leakage inductance is m easured at the switching frequency on the primary winding with all other windings shorted. then, the snubber resistor with proper rated wattage should be chosen based on the power loss. the maximum ripple of the snubb er capacitor voltage is obtained as: s sn sn sn sn f r c v v ? ? ? ? (43) in general, 5~20% ripple of the selected capacitor voltage is reasonable. in the snubber design in this section, neither the lossy discharge of the inductor nor stray capacitance is considered. in the actual converter, the loss in the snubber network is less than the designed value due to this effect.
AN-9735 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/12/11 8 design example using fsfr1317 table 2. cable compensation application device input output led bulb fsez1317my 90v ac ~ 265v ac (50 ~ 60hz) 4.2w (12v/0.35a) description symbol value unit system specifications input minimum line input voltage v line min 90 v ac maximum line input voltage v line max 265 v ac line frequency f l 60 hz setting output voltage v o 12 v output voltage at point b v o@b 8.40 v minimum output voltage v o min 3 v normal output current i o n 0.35 a output diode voltage drop v f 0.55 v normal switching frequency f s 50 khz switching frequency between point b and point c f sr 33 khz estimated efficiency input efficiency 0.75 w output secondary-side efficiency s 0.91 input power p in 5.60 input power of transformer p in_t 4.62 efficiency at point b @b 0.74 secondary-side efficiency at point b s@b 0.89 input power at point b p in@b 3.99 input power of transformer at point b p in_t@b 3.30 efficiency at point c @c 0.66 secondary-side efficiency at point c s@c 0.80 input power at point c p in@c 1.58 input power of transformer at point c p in_t@c 1.31 determine dc link capacitor & dc link voltage range input dc link capacitor c dl 9.40 f output minimum dc link voltage v dl min 90.87 v maximum dc link voltage v dl max 374.77 minimum dc link voltage at point b v dl@b min 102.64 minimum dc link voltage at point c v dl@c min 118.12 determine the transformer turn ratio input rectifier output voltage v ro 70.0 v maximum v dd vdd max 24.0 minimum v dd vdd min 5.5 v dd ripple in burst mode vdd ripple 2.5 v dd diode drop voltage v fa 0.70 n a /n s ratio n a /n s 0.80 output mosfet overshoot voltage v os 70.00 n p /n s ratio n p /n s 5.58 minimum n a /n s ratio 1 n a /n s min1 0.69 minimum n a /n s ratio 2 n a /n s min2 0.39 determine minimum n a /n s ratio n a /n s min 0.69 determine maximum n a /n s ratio n a /n s max 0.98
AN-9735 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/12/11 9 description symbol value unit transformer design input non conduction time at point b t off@b 5.00 s transformer core cross-sectional area a e 20.10 mm 2 maximum flux density b sat 0.30 t determine secondary-side turns n s 20 turns output mosfet conduction time at point b t on@b 4.91 s transformer primary-side inductance l m 1.92 mh peak drain current i ds pk 0.31 a minimum primary-side turns n p min 98.93 turns determine primary-side turns n p 112 turns determine auxillary winding turns n a 16 turns final n p /n s ratio n p /n s 5.60 final n a /n s ratio n a /n s 0.80 mosfet conduction time t on 6.57 s inductor discharge time t dis 8.49 s non-conduction time t off 4.95 s mosfet conduction time at point c t on@c 3.31 s inductor discharge time at point c t dis@c 19.65 s non conduction time at point c t off@c 7.35 s selection switching device output mosfet maximum drain-source voltage v ds max 514.77 v mosfet rms current i ds rms 0.10 a maximum diode voltage v f 78.92 v maximum diode rms current i f 0.65 a setting output voltage & current input vs low-side resistor r2 33.00 k ? current-sensing resistor 1 r sense1 3.9 ? current-sensing resistor 2 r sense2 3.6 ? real vs high-side resistor r1_ real 100 k ? output vs high-side resistor r1 93.72 k ? current-sensing resistor r sense 1.92 ? real output voltage setting vo 11.34 v real current-sensing resistor rs 1.872 ? real output current setting io 0.36 a design rcd snubber stage input leakage inductance of primary side l lk 50 h rectifier output voltage v ro 70 v mosfet overshoot voltage v os 70 v output snubber voltage v sn 141 v snubber capacitor ripple voltage v sn 28.11 v resonance time t s 0.22 s power dissipation in snubber resistor p sn 0.24 w snubber resistor r sn 82.26 k ? snubber capacitor c sn 1.22 nf
AN-9735 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/12/11 10 design summary using fsfr1317 figure 11. schematic for led bulb l n l1 1mh + c4 4.7uf/400v + c5 4.7uf/400v c2 open r4 open output gnd u1 fsez1317 vdd 2 hv 7 gnd 3 comr 4 cs 1 drain 8 vs 5 + c8 220uf/16v c14 2.2n/1k l4 0 r3 100k3216 c1 4.7n/1kv d5 1n4007 d7 1n4007 d6 egp20d + c6 10uf/50v t1 1 4 3 2 8 5 r13 3r6/3216 r14 3r9/3216 u2 mb6s - 4 + 3 l 2 n 1 f1 250v/1a r9 100k/2012 r15 33k/2012 c7 47pf/2012
AN-9735 application note ? 2011 fairchild semiconductor corp oration www.fairchildsemi.com rev. 1.0.0 ? 4/12/11 11 transformer for led bulb core : ee-16 (material: pc-40) bobbin : 8-pin figure 12. transformer specifications and construction table 3. winding specifications no. winding pin (s f) wire turns winding method 1 np 2 ? 1 0.12 1 112 ts solenoid winding 2 insulation: polyester tape t = 0.025mm, 3 layer 3 ns 8 ? 5 0.32 (tex)1 20 ts solenoid winding 4 insulation: polyester tape t = 0.025mm, 3 layer 5 naux 3 ? 4 0.15 1 16 ts solenoid winding 6 insulation: polyester tape t = 0.025mm, 3 layer table 4. electrical characteristics pin specification remark inductance 1 ? 2 1.90mh 10% 1khz, 1v
AN-9735 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/12/11 12 related datasheets fsez1317 ? primary- side regulation pwm with power mosfet integrated datasheet fan103 ? primary-side regulation pwm controller datasheet an-8033 ? design and application of primary-side regulation (psr) pwm controller disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described he rein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as criti cal components in life support devices or systems without the express written approval of the preside nt of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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